Scanned display device



Oct. 21, 1969 ANWANG 3,474,437

SCANNED DISPLAY DEVICE Filed June l5. 1966 2 Sheets-Sheet 1 l l 1 i 1 1 1 1 a l 1 1 l l I N L NN/ oN/ n m5 @mi momnom 556mm v V M9255 3.5@ Vod zoEwon 1 Q LNV w |I Il rr Il 1 l l 1 i l l l I l l I l l l I l l l 23,56 z 553mm o. m N me? m v m N m .wol .moa .moa .moa .moa .moa .wol .wom .wol .wou zool 5 Q m9 Q. EE EN E 2mm www@ m9@ 2mm ow mm o.

Q ov ou Ow GU A Q ou ou 0U N Q o5 me S @n m@ v me NQ Oct. 21, 1969 AN -WANG SCANNED DISPLAY DEVICE 2 Sheets-Sheet 2 Filed June 15, 1966 Wlmlvlllllwl N NNN www is United States Patent O 3,474,437 SCANNED DISPLAY DEVICE An Wang, Lincoln, Mass., assigner to Wang Laboratories, Inc., Tewksbury, Mass., a corporation of Massachusetts Filed June 15, 1966, Ser. No. 557,748 Int. Cl. G0811 23/00; H01k 1/60 U.S. Cl. 340-324 7 Claims ABSTRACT F THE DISCLOSURE This invention relates to display units and more particularly to symbol display devices particularly adapted for use with high speed computing devices.

Contemporary computing devices are capable of performing data manipulations at extremely high speeds, frequently in the order of micro-seconds. Such high speed computing devices can be manufactured relatively inexpensively. However, output devices such as displays that are compatible with such high speed computing devices are comparatively expensive. A particular problem arises in connection with a symbol display that is compatible with such computers. A useful display device is a gasfilled cold cathode indicator tube (colloquially termed a Nixie Tube). Display arrangements employing such tubes have heretofore been relatively expensive and hence their application has been limited to relatively complex and costly computing systems.

An object of this invention is to provide a simplified and relatively inexpensive display arrangement which employs symbol display elements of the cold cathode type.

Another object of the invention is to provide a novel and improved display unit that incorporates both symbol and radix point display.

Still another object of this invention is to minimize the circuitry necessary to display information in a display device and to substantially reduce the number of lines necessary to convey information between the computing device and the display device.

It is a further object of this invention to reduce the size and the cost of a display device while minimizing the number of lines and the circuitry without sacrificing the speed, clarity or ease of operation of the display device.

The invention features a multi-position display device which includes a plurality of indicators, one for each position of the display device; each indicator includes a common electrode and a plurality of symbol electrodes. Symbols to be displayed are stored in a storage register having a stage corresponding to each of the positions in the display device. Control means are provided to supply signals to read out the signals in the stages of the storage register and to energize the common electrode of the indicator at the one of the positions in the display device corresponding to the stage of the Storage register which is being read out.

In a preferred embodiment the indicators are gas-lilled cold cathode indicator tubes and the symbols represented by the cathodes are decimal numbers. Also associated with the display are decimal point indicators in the form of neon tubes. Thus, each indicator tube has ten cathodes.

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The corresponding cathodes of the several tubes are connected together so that all are energized simultaneously. Only o ne anode is energized at any one time, that anode corresponding to the stage of the storage register than being read out so that the only symbol that is illuminated is in the tube corresponding to that stage. The anodes are energized sequentially and during each cycle one neon tube is energized using portions of the control circuitry common with the symbol display. A further feature of the control circuitry is the provision of inhibit signals which utilize portions of the control circuitry common with other functions and energize the symbol indicator tubes in a manner indicating that the corresponding stage of the storage register is cleared (has no decimal Value in it).

In preferred embodiments the control means includes a stepping register for energizing the common electrodes of the indicators and a clock pulse source for synchronizing the reading out of the storage and stepping registers.

Other objects, features, and advantages will appear from the following description of a preferred embodiment of the invention, taken together with the attached drawings thereof, in which:

FIG. 1 is a block diagram of the remote display device and a portion of the computing device of the invention; and

FIG. 2 is a schematic of a portion of the remote display device of FIG. 1.

In FIG. 1 remote display device 10 is connected t0 computing device 12 by two cables 14 and 16 of four wires each. Only four wire cable is needed because the information in storage register 18 and in position register 20 is in binary code; binary code permits sixteen discrete pieces of information to be conveyed using four signals. Clock pulse source 22 simultaneously supplies pulses to position register 20 and storage register 18 at a rate which completely cycles both storage register 8 and position register 20 one hundred and forty times a second.

Position register 20 is a twelve stage register or counter with non-destructive read-out, and it stores twelve combinations in binary code corresponding to the twelve display positions of FIG. 1, as follows:

CHART I Binary Position register code stage representations Pulses from clock pulse source 22 step position register 20 causing the binary codes indicating positions 1-12 to be successively, repeatedly transmitted on cable 16.

Storage register 18 is a twelve stage register containing an indication of the placement of the radix point in the first stage, an indication of the sign (-lor in the second stage, and numbers in stages 3-12. An inhibit signal, represented by binary code llll, may be placed in any stage of storage register 18. When this signal appears in storage register 18 all positions in remote display device 10 will be blanked. The inhibit signal is used to clear the display and to prevent a present display from Binary Codes Which May Appear There Meaning of Codes Storage Register Stage:

(2) 0 0 Plus (-1-) 2 or Minus l Same as stages 3-12. 2 Radix Point Locatlon.

Since numbers of the base ten are displayed by this embodiment, the radix point is a decimal point and will be so referred to hereafter.

Clock pulse source 22 controls the display by pulsing storage register 18 simultaneously with position register 20, thereby causing the binary codes in stages 1-12 to be successively, repeatedly transmitted on cable 14 in time with those from position register 20 on cable 16. Referring to Chart II, stages 3-12 may contain the binary codes for numbers 0-9 in any order; the binary codes for 0 and 9 are used to indicate plus (-1-) and minus signs, respectively, when they appear in stage 2 of stor age register 18.

Signals from storage register 18 are transmitted to display decoder 24 via cable 14 and are there decoded. A set of four binary signals on cable 14 will energize one of the eleven outputs of display decoder 24. Any one of the ten lines in cable 26 may be energized if the code sent represents one of the numbers 0-9; the line 30 would be energized if the inhibit code is received. Each line in cable 26 is connected to each of the positions 1-12, with the exception of position 2, to which are connected only the 0 line (-1-) and the 9 line That is, when position 2 is energized by position register 20, the second stage of storage register 18 is being read out and that stage contains only a 0 (0000) or a 9 (1001), Chart II, depending on whether the value in the storage register 18 is positive or negative.

Signals from position register 20 are transmitted to position decoder 28 via cable 16 and are there decoded. A set of four binary signals on cable 16 will energize one of the twelve outputs 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, and 54 of position decoder 28 that connect to positions 1-12 respectively.

Line 32 connects at position 1 to all the anodes 56 of the ten neon tubes 58, 60, 62, 64, 66, 68, 70, 72, 74, and 76. These neon tubes represent the decimal point in the ten places where it may appear. Neon tube 58 is at the left of position 3; neon tube 40 is at the left of position 4; neon tube 62 is at the left of position 5 and so on, neon tubes 64, 66, 68, 70, 72, 74, and 76 being similarly placed with respect to positions 6-12. Although the ten neon tubes are not at position 1, but at the ten places described above, for clarity they are shown as receiving inputs at their anodes 56 on lines Dl-Dm. The cathode 78 of each of the neon tubes is connected to a diierent one of the lines in cable 26, as indicated in Chart III.

CHART III Neon tube: Cathode connection 58 0 line 60 1 line 62 2 line 64 3 line 66 4 line 68 5 line 70 6 line 72 7 line 74 8 line 76 9 line Thus, when line 32 is energized the signals on cable 14 will energize a number line in cable 26, which will cause one of the neon tubes to glow displaying the decimal point at the desired location.

Each position 2-12 contains a gas-filled, cold cathode indicator tube 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, and 100, respectively, which has its anode connected to lines 34, 36, 38, 40, 42, 44, 46, 48, 50, S2, and 54, respectively. Indicator tube 80 has only two cathodes, one shaped as a and connected to the 0 line, the other shaped as a and connected to the 9 line. The rest of the indicator tubes 82, each have ten cathodes, one shaped as each of the numbers 0, l, 2, 3, 4, 5, 6, 7, 8 and 9, and each cathode is connected to the line carrying the signal corresponding to its shape. While numbers are displayed in the preferred embodiment, it is clear that any symbols may be displayed. The single anode in each indicator tube is common to all the cathodes in that indicator tube. Restating the connection of the cathodes of the indicator tubes:

Like cathodes are connected in parallel;

The cathode is paralleled with the 0 cathodes;

The cathode is paralleled with the 9 cathodes;

The cathode of each neon tube is connected in parallel with a number cathode of the indicator tube immediately to its right, FIG. 1.

The location of the neon tube determines which number cathode of its respective indicator tube it connects to. From left to right, the first neon tube 58 connects with the 0 cathode of indicator tube 82, the second neon tube 50 connects with the 1 cathode of indicator tube 84, and so on.

In operation, clock pulse source 22 emits pulses to cycle position register 20 one hundred and forty times a second causing the anodes at positions 1-12 (lines 32-54) to be energized at the same rate. Simultaneously, clock pulse source 22 emits pulses to cycle storage register 18, one hundred and forty times a second. The outputs of clock pulse source 22 are timed so that position register 20 and storage register 18 are pulsed in unison. The cycle evolves as follows:

Line 32 is energized and one of the number lines 0-9 is energized displaying the decimal point;

Line 34 is energized and either the 0 line or 9 line is energized displaying a or Line 36 is energized and one of the number lines 0-9 is energized displaying a number 0-9.

This continues until line 54 at position 12 is energized and the last stage of storage register 18 is read out. Then the cycle begins again. The display continues thusly with the location of the decimal point, the sign, and the numbers changing as the information supplied to storage register 18 from the computing operations changes.

A schematic of the circuits of the display decoder 24 and the position decoder 28 is shown in FIG. 2. The four lines in cable 16 are labeled for the signals which they carry P1, P2, P4, and P11, said signals corresponding to the 2, 21, 22, and 23 positions in binary code, respectively. Circuit 102 receives P1 signals and inverts them making available 151 signals. Three identical circuits, not shown, similarly invert P2, P4, and P8 to provide P2, P4, and P8. These eight signals are provided to twelve circuits corresponding to positions 1-12, FIG. l, in combinations of four. Those circuits associated with positions 2-12 are identical, so only three of them have been shown, viz. circuits 104, 106, and 108. Circuit 110 associated with position 1 (decimal point) differs only slightly as will be pointed out in the following discussion.

Inverter circuit 102 consists of a PNP transistor 112 6 70, 72, 74, and 76 through a 10K@ resistor 160, rather than to the anode of a single indicator tube as in the other circuits.

The volt bias on resistor 148 keeping transistor 126 conducting can only be overcome when each of the diodes 154 in AND gate 150v receives -10 volts on its anode. If any one of the anodes receives a 0 volt signal, it will conduct placing the -10 volt drop across resistor 156 and keeping point 162 at 0 volts. But if all anodes receive a -10 volt signal there is no conduction through diodes 154 and point 162 is at -10 volts. This is reflected at base 146 and switches oir' transistor 126. The cornbination of Ps and s required at the AND gates 150 of each of the circuits corresponding to positions 1-12, their voltage levels, and the binary codes represented by them are set forth in Chart IV.

CHART IV P voltages P Voltages Binary n Code P1 P2 P4 P5 P1 P2 P4 P8 Circuit AND Gate Combination Position:

1 0 0 0 0 0 0 0 0 -10 -10 -10 -10 QQ P4 P4 4 Pg 2 1 0 0 0 -10 0 0 0 0 -10 -10 -10 1 0 1 P4 Pg P4 Pg 3 0 1 0 0 0 -10 0 0 -10 0 -10 -10 1 P1 Pg P4 PB 4 1 1 0 0 -10 -10 0 0 0 0 -10 -10 N0tsho\vn P1 P4. P4 Pg 5 o 0 1 0 o o -10 o -10 -10 0 -10 do P1 P2 P4 P2' 6 1 0 1 0 -10 0 -10 0 0 -10 0 P2 P4 Pg 7 .0 1 1 0 0 -10 -10 0 -10 0 0 Pg' P4 P2 8 1 1 1 0 -10 -10 -10 0 0 0 0 Pz P4 lss 9 0 0 0 1 0 0 0 -10 -10 -10 -10 P4 154 P11 10 1 0 0 1 -10 0 0 -10 0 -10 -10 P2 P4 P2 11 0 1 0 1 0 -10 0 -10 -10 0 -10 P2 P4 P1 12 1 1 0 1 -10 -10 0 -10 0 0 -10 P4 P4 P1 which receives the P2 signal on its base 114 through an 18K@ signal resistor 116; base 114 is biased by +10 volts through ISOKQ bias resistor 118. Emitter 120I is connected to ground and collector 122, which provides the 151 output, is connected to +10 volts through a 12Kz load resistor 124. The bias on base 114 maintains transistor 112 in a non-conducting state. Thus a P1 signal of 0 does not aiTect the non-conducting state of transistor 112 leaving the P1 output at essentially -10 volts, the voltage level at resistor 124. Whenever a +10 volt P1 signal appears, transistor 112 conducts driving collector 122 to ground and causing a 0 volt output. Whichever value P1 is then, P1 will be the other.

Circuit 104 contains two NPN transistors 126 and 128. The collector 130 of transistor 128 connects to B+, +250 volts, through an ISKQ resistor 132. Base 134 connects to B+ through a 270K@ resistor 136 and to collector 138 of transistor 126 through resistor 140. Normally conducting transistor 126 holds base 134 of transistor 128 sufficiently negative with respect to collector 130 to prevent conduction. Only when transistor 126 ceases to conduct, permitting base 134 to rise to the B+ level, does transistor 128 conduct completing a circuit through either the or cathode of indicator tube 80, whichever one is energized at that time. The emitter 144 of transistor 126 connects to ground; base 146 connects to +10 volts through a 1001452 biasing resistor 148 and to a four input AND gate 150 through a 27KQ signal resistor 152. AND gate 150 contains four diodes 154 having their cathodes connected in parallel and biased negatively by +10 volts through 27KS2 signal resistor 156. Unless the correct combination of signals is supplied to AND gate 150 the bias at the cathodes of diodes 154 is not overcorne and transistor 126 is not switched oi. All the circuits associated with positions 1-12 viz. circuits 104, 106, 108 and those not shown are identical in construction and function with circuit 104. And circuit 110 diiers only in that 270KSZ resistor 136 is replaced by a 680KQ resistor 157, collector 130 has a 33KQ resistor 158 between it and resistor 132, and emitter 142 is connected to the anodes 56 of all the neon tubes 58, 60, 462, 64, 66, 68,

Display decorder 24 is shown in the lower half of FIG. 2. The four lines within cable 14 are labeled for the signals which they carry N1, N2, N4, and N11, said signals corresponding to the 2, 21, 22, and 23 positions in binary code, respectively.

Circuit 164 receives N1 signals and inverts them making available N1 signals. The N1 line is connected to base 166 of transistor 168 through a IZOKQ resistor 170; and base 166 is biased against conducting by +10 volts applied through a K@ resistor 172. Emitter 174 connects to ground and collector 176, where 1 appears, is connected to -12 volts through a 3.3K@ resistor 178. The bias on base 166 maintains transistor 168 in a non-conducting state. Thus a 0 signal on N1 does not alect the non-conducting state of transistor 168; it leaves the N1 output at essentially -12 volts. the voltage level at resistor 178. Inverter circuit connected to N2 and the inverter circuits, not shown, connected to N4 and N8 are identical in function to circuit 164 and diter in structure only in that 3.3K@ resistor 178 is replaced by a 1.8K@ resistor 182 and connects to -10 volts rather than -12 volts. The slight d iierence between the resistance values is necessitated by the difference in loads encountered by the other N signals.

The circuits that energize the cathodes of the indicator tubes are divided into two groups, those that connect to even number cathodes and those that connect to odd number cathodes. Each of the even number circuits, 184 connected to 0 shaped cathodes and the shaped cathode, 186 connected to 6 shaped cathodes, and 188 connected to 8 shaped cathodes are connected to ground on bus 190 through circuit 192. The circuits that are `connected to the 2, 3, 4, and 5 cathodes are not shown; they are identical to those shown. Each of the odd number circuits, 194 connected to the 1 shaped cathodes, 196 connected to the 7 shaped cathodes, and 198 connected to the 9 shaped cathodes and the shaped cathode are connected to ground on bus 200 through circuit 192.

Circuit 192 receives an N1 signal through 12K@ signal resistor 202 at the base 204 of transistor 206; transistor 206 has its collector 208 connected to even bus 190 and has its emitter 210 connected to ground through a IOOKQ limiting resistor 212. Similarly, circuit 192 receives 'l signals through 12Kn signal resistor 214 at the base 216 of transistor 218; transistor 218 has its collector 220 connected to the odd bus 200 and has its emitter 222 connected to ground through resistor 212. Bases 204 and 216 are biased by volts through 33KQ resistors 224 and 226, respectively.

Although inhibit circuit 228 is switched by a four input AND gate 230, all the cathode energizing circuits 184, 186, 188, 194, 196, 198, and those not shown, have only three input AND gates 232. This is accomplished by using the N1, 1 signals to energize the even bus 190 or odd bus 200, respectively, then using N2, N4, N8, Z, N4 and position 2, depending upon which position is energized at that moment. Had position 1 been energized, (circuit 110 switched on), the anodes 56 of all the neon tubes representing decimals would have been energized. The circuit of only one of these neon tubes, tube 58, would have been completed to ground; thus the decimal point to the left of position 3 would be lighted.

The number and type of characters displayed and the number of positions in the display may be varied without departing from the scope of the invention. Other embodiments will occur to those skilled in the art and are within the following claims.

What is claimed is:

1. A multiposition display device comprising:

s Combinations to switch the cathode energizing circuits. a' luralgy .(fdirslt mhc'fltors one for each Said Pos1' This implementation also permits each three input AND En qdsl t sfay evicel d. l d gate 232 to serve an even and an odd cathode circuit. A eac sal rs .m lcator mc u mg a common e ectro e l b. fN N N t andaplurahty of symbol electrodes, parmi] ar com mation o 2 .1 .8 2 4 N8 at qmpis a first register for supplying signals identifying ones of to switch an even and an odd clrcult but only the c1rcu1t 20 d 1 t d t b d hich is connected to the energized bus 190 or 200 will Sal commfm e ec ro eS-o e energize W a second register for storing symbols to be displayed, be swltched' said second register having a stage corresponding to The N and N Combmatlolsfequlfed t0' SVYltfJll AND each of said positionsinsaid display device, gateS 230 and 232 Corresponding t0 the mhlbllllg and means for reading out said first and second registers in cathode circuits, their binary codes, and their voltage timed relation with each other and levels are set forth in Chart V. control means for supplying signals to read out the CHART V N Voltage `Voltage Binary Code Nl N2 N4 Ng N, z i circuit AND Gate Combination 1 1 1 +10 +10 +10 +10 0 0 0 0 gg Ni Ni Ni Na 0 o 0 0 0 0 0 +10 +10 +10 +10 E Ni N1 Ni Na 0 0 0 +10 0 0 0 0 +10 +10 +10 g5 Ni Nr N4 NB 1 0 o 0 +10 0 0 +10 0 +10 +10 Notshown. N1 Nr N4 Nr 1 0 o +10 +10 0 0 o 0 +10 +10. -do N1 Ni N4 N8 0 1 0 0 o +10 0 +10 +10 0 Ni Ni Nt 0 1 0 +10 0 +10 0 0 +10 0 Nr Ni Nt 1 1 0 0 +10 +10 0 +10 0 0 Nr Ni Ni 1 1 0 +10 +10 +10 0 0 o 0 Nr N4 N8 0 0 1 0 0 0 +10 +10 +10 +10 Nr Ni Ns The base 234 of transistor 236 in inhibit circuit 228 is held at approximately 1/3 of the +10 volt bias by 27KQ biasing resistor 238 and 12K@ signal transistor 240 when the specified combination is not present at AND gate 230. With one or more diodes 242 receiving a 0 volt input, that diode will conduct resulting in the 1A, distribution of the voltage applied to resistor 238. But when the proper combination of inputs is present, all inputs are +10 volts, there is no conduction through diodes 242, and base 234 is driven positive switching on transistor 236. Switching on transistor 236 connects line 30 to ground; this drives collector 130 in circuit 110 to ground and connects collectors 130 of the remaining position circuits to ground through line 244 and 33K@ limiting resistor 158. This condition prevents energization of any of the position circuits thereby blanking all display.

Circuit 184, the 0 cathode energizing circuit, is typical of all the cathode energizing circuits with the exception that it, and the 9 cathode energizing circuit 198, has an extra connection for energizing that and cathodes. As was the case with circuit 228, if the proper signal is lacking at any one of the diodes 242 that diode will have a zero at its input, willA conduct, and will cause a distribution of the +10 volts applied to 33K@ resistor 248 of approximately 1A, 2/3 with respect to base 250 of transistor 252; the 1/3 is across IZKQ signal resistor 254. When the proper combination of inputs is provided to AND gate 232, point 256 is at -l-lO volts and transistor 252 is switched on. With regard to circuit 184 in particular, this means that all 0 cathodes. and the -lcathode, are connected to ground through transistor 252 and a 0 appears at the one of positions 3-12, or a -iat signals in said stages of said second register, all of said symbol electrodes corresponding to the symbol stored in the stage being read-out being energized simultaneously, and for concurrently supplying signals to energize the common electrode of the first indicator at the one of said positions corresponding to the said stage being read out comprising:

first decoder, responsive to signals from said first register, for energizing individual ones of said common electrodes, said first decoder comprising:

a plurality of first switching circuits for energizing said common electrodes of said first indicators, each of said first switching circuits including,

first switching device having an output circuit connected to a said common electrode of one of said first indicators, and an input electrode biased to keep the output circuit of said first switching device from conducting,

and a first AND gate connected to said input electrode, said first AND gate delivering an output signal, upon receiving all proper inputs, which overcomes said bias on said input electrode sufcient to enable said first switching device to conduct, and a second decoder, responsive to signals from said second register representing symbols to be displayed, for energizing the one of said symbol electrodes in each of said indicators which the signals from said first register represent, said second decoder comprising: plurality of second and third switching circuits for energizing said symbol electrodes of said indicators, each said switching circuit including a switching device having a first output circuit connected to all similarly shaped said symbol electrodes of said indicators, and an input electrode biased to keep the output circuit of said switching device from conducting,

a fifth switching circuit for inhibiting operation of said first decoder including,

a sixth switching device having an output circuit connected to said first decoder, and an input electrode biased to keep said sixth switching device from conand a plurality of second AND gates, each said secducting, and

ond AND gate being connected to the input eleca third AND gate connected to said input electrode of trode of the switching device of one of said second said sixth switching device, said third AND gate switching circuits and to the input electrode of the delivering an output signal, upon receiving all proper switching device of one of said third switching cirinputs, which overcomes said bias on said input eleccuits, and delivering an output signal, upon receivtrode and causes said sixth switching device to ing all proper inputs, which `overcomes said bias on conduct, said input electrodes of the switching devices con- 4. The apparatus of claim 1 in which said first indicanected to it, tors are gas-filled cold cathode tubes, and said syma first common line connected to said second switch- Ybol electrodes .are shaped to represent symbols t0 ing circuits and a second common line connected to be displayed, said third switching circuits, 5. The apparatus of claim 1 further including: a fourth switching circuit for selectively energizing said a plurahty of Second indicators, ea'ch having a first first and Said Second coInInon iineS including, electrode and a second electrode, all said first eleca fourth Switching device having au Output circuit Con 20 trodes being connected together, and being energized nected to said first common line, and an input elecin response to Signals from Said Control means, trode biased t0 prevent conduction in Said Output each of said second electrodes being connected to a cifcuit unieSS a predetermined Signal iS Present at different symbol electrode of said first indicators. said input electrode, and 6. The apparatus of claim S in which said second ina ifth switching device having an output circuit condicators are gas discharge tubes.

nected to said second common line, and an input electrode biased to prevent conduction in said output circuit unless a predetermined signal is present at said input electrode,

and logic responsive to signals from said second register to selectively overcome the bias on the input electrodes of said fourth and fifth switching devices and in conjunction with one of said second AND gates to cause one switching device of said second and third switching circuits to conduct.

2. The apparatus of claim 1 wherein each said switch- 7.V The apparatus of claim 5 wherein one of said first switching circuits has rall of the first electrodes of said second indicators connected to the output circuit of a switching device of said one first switching circuit.

References Cited UNITED STATES PATENTS 3,387,269 6/1968 Hernan et al 340-324 JOHN W. CALDWELL, Primary Examiner ing device is a semiconductor having an output circuit that includes rst and second output electrodes.

3. The apparatus of claim 1 in which said second decoder further includes:

M, M. CURTIS, Assistant Examiner U.S. C1. X.R. 

